Product Details
Gated J-K Master –Slave Flip Flop 14PIN DIP
Specifications
- Logic Family:TTL (74xx series)
- Package:14-pin DIP (through-hole)
- Number of Flip-Flops:2 (dual)
- Type:Gated J-K master–slave flip-flop
- Triggering:Clocked, master–slave configuration
- Outputs:Q and Q̅ (complementary)
- Asynchronous Inputs:Preset and Clear (active LOW, typical)
- Supply Voltage (Vcc):75 V – 5.25 V (nominal 5 V)
- Absolute Max Vcc:~7 V
- Input Voltage Range:–0.5 V to Vcc
- Logic HIGH (VIH):≥ 2.0 V
- Logic LOW (VIL):≤ 0.8 V
- Output HIGH (VOH):≥ 2.4 V
- Output LOW (VOL):≤ 0.4 V
- Propagation Delay:~20–35 ns (typical, depends on load)
- Power Dissipation:~10–25 mW per flip-flop (typical TTL)
- Operating Temperature:0 °C to 70 °C (commercial range)
Typical Applications
- Counters and registers
- Frequency division
- State machines
- Control logic
- Toggle and memory elements
Additional Information
| Device | Gated J-K Master |